Flash analog-to-digital converters (ADCs) achieve the highest conversion rates because an input voltage is compared with all quantization levels in parallel. However, the resolution of flash ADCs is limited by circuit area and input capacitance because of the exponential relationship to the number of comparators required. More recently, time interleaving of multiple ADCs has been applied to address these limitations. According to one approach, several high-resolution, lower speed ADCs are operated together in a time interleaved fashion to provide a high speed, high resolution ADC. Such ADC structure, however, introduces sampling noise and, because of inconsistent sampling interval timing may introduce intermittent and semi-random noise into the sampling process.